The present invention generally relates to a flash memory device, and more particularly, to a flash memory device capable of preventing disturbance in a read operation using self-boosting.
With the increasing market for mobile and multimedia products, there is an increasing demand for high-capacity non-volatile memories, such as electrically programmable and erasable flash memories, which can retain data even when power is interrupted. As a result of this demand, various flash memory types have been developed.
Commonly used flash memory types include NOR flash memory and NAND flash memory, which employ different arrangements of unit memory cells. The NOR flash memory has a higher programming rate due to using a channel hot electron (CHE) injection program mechanism and has better random access properties due to its cell array structure. However, NOR flash memory requires a greater chip area per memory cell than NAND flash memory. As a result of its greater storage density, NAND flash memory has a lower cost per memory bit than NOR flash memory. Additionally, NAND flash memories typically have increased endurance as compared to NOR flash memories. As a result, NAND flash memory is typically used for large capacity storage devices where random access time is not important.
NAND flash memory cells store data by manipulating the amount of electrical charge on a floating gate. The floating gate is located between a control gate and a channel region in the semiconductor substrate. The control gate is used to manipulate the level of electrical charge on the floating gate. The control gate is connected to a word line whereby the voltage level of the control gate can be controlled. By manipulating the voltage level of the overlying control gate relative to the underlying channel region, electrons can be transferred to or from the floating gate, thereby changing the electrical charge of the floating gate. Once the charge level of the floating gate has been set, the floating gate tends to retain the charge in the absence of a sufficiently high voltage potential differences necessary to cause subsequent transfer of electrons to or from the floating gate, thereby providing the ability to retain data when power is interrupted. Because the channel region is subjected to different electrical fields based upon the level of charge of the floating gate, the threshold voltage of the memory cell will vary according to the level of charge of the floating gate, thereby providing a way of determining the state of the memory cell. Memory cells of a NAND flash memory are in an erased state or a programmed state.
Memory cells of an erased state have a relatively low threshold voltage distribution, for example, lower than approximately 0 V. On the other hand, memory cells of a programmed state have a relatively high threshold voltage distribution, for example, higher than approximately 0 V.
A read operation for determining the state of a selected memory cell is generally performed on a page basis. In order to determine the state of the selected memory cell, the bit line of the memory cell string containing the selected memory cell is precharged to, for example, approximately 1 V to approximately 2 V. Next, the drain select transistor and the source select transistor for the selected memory cell string are turned on to form an electrical path in the memory cell string containing the selected memory cell. A pass voltage Vpass is applied to the word lines connected to the control gates of the unselected memory cell transistors in the selected memory cell string such that the channels of the unselected memory cells are turned on regardless of a state of the unselected memory cells.
Since all the channels included in the selected memory cell string except the channel of the selected memory cell are known to be turned on, a current will flow or not through the entire cell string depending on whether the channel of the selected memory cell is turned on or off, which in turn depends upon the state of the selected memory cell. When the selected memory cell is in an erased state, the selected memory cell channel is turned on, and a current will flow through the entire cell string. As a result, the precharged bit line will be discharged to approximately 0 V on account of the bit line being connected to the drain line by way of the open channels of the selected memory cell string. On the other hand, when the selected memory cell is in a programmed state, the selected memory cell channel is turned off, a current does not flow through the cell string, thereby maintaining the precharged voltage of the bit line. As a result, it can be determined whether the selected memory cell is in an erased state or in a programmed state depending on whether the precharged voltage of the bit line decreases to approximately 0 V.
However, the application of the pass voltage Vpass to the control gates of the unselected memory cells may result in the occurrence of a read disturbance. A read disturbance occurs when there is an unintentional altering of the state of an unselected memory cell during a read operation. While the use of higher pass voltages during a read operation results in increased current flow in the selected memory cell string due to decreased resistance of the affected channels, thereby making the determination of the state of easier by more quickly discharging the bit line, the use of higher pass voltages may cause a read disturbance. When the pass voltage becomes larger than a predetermined magnitude, the resulting voltage potential differences may result in the transfer of electrons to or from the floating gate of the unselected memory cell, thereby inadvertently altering the state of the unselected memory cell.
Inadvertent alteration of the state of an unselected memory cell can also occur during a program operation. During a program operation, a high program voltage from approximately 15 V to approximately 20 V is applied to the word line connected to the cell selected to be programmed and the bit line of the selected cell is grounded. As a result, the charge on the floating gate of the selected memory cell is altered, thereby programming the selected memory cell. Unfortunately, because the word line is also connected with the control gates of memory cells not selected for programming, these unselected memory cells may be inadvertently programmed despite the fact that their bit lines were not grounded.
In order to prevent this inadvertent programming, self-boosting, where a ground voltage (0 V) is applied to the bit line of the memory cell to be programmed and a power voltage Vcc is applied to a bit line of a memory cells not to be programmed, is used. In such a voltage state, the ground voltage is transferred to the channel of the memory cell to be programmed, thereby enhancing the resulting voltage potential differences used to program the selected memory cell. Also, a select transistor of the unselected bit line is turned off thereby isolating the memory cells connected to unselected bit lines and placing the channel regions of these unselected memory cells into a floating state. By using self-boosting, voltage potential differences between the floating gates of unselected memory cells and surroundings can be reduced, thereby reducing the potential for the occurrence of a program disturbance.
Self-boosting can also be used for reducing the potential for an inadvertent memory state alteration during a read operation. In a read operation using self-boosting, a voltage higher than a power voltage Vcc is applied to unselected bit lines and source lines, while the selected source line is grounded. The channels of the unselected memory cells are thereby boosted, which decreases voltage potential differences between the gates and the channels, thereby restraining read disturbances. That is, although a pass voltage higher than approximately 5.5 V is applied to the control gates of the unselected memory cells, eventually a bias corresponding to a difference between the pass voltage and the power voltage Vcc is applied, thereby preventing undesired programming of unselected memory cells during the read operation.
Meanwhile, in order to perform a self-boosting read operation smoothly, a common source line CSLe of an even bit line BLe and a common source line CSLo of an odd bit line BLo are separated from each other. That is, when a selected memory cell is connected to the even bit line BLe and all memory cells connected to the odd bit line BLo are in an erased state, a power voltage Vcc applied to the odd bit line BLo may be discharged through a common source line CSL. However, when the common source line CSLe of the even bit line and the common source line CSLo of the odd bit line are separated from each other, while the common source line CSLe of the even bit line is grounded, a bias equal to or higher than the power voltage Vcc applied to the odd bit line BLo is applied to the common source line CSLo of the odd bit line such that a voltage applied to the odd bit line BLo is not discharged through the common source line CSLo.
However, in the self-boosting read operation, when a short occurs between the common source line CSLe of the even bit line and the common source line CSLo of the odd bit line or between a source line of an even or odd bit line and a bit line due to defect generated during an interconnection process, self-boosting cannot be used and a chip fail may occur. As cell size decreases due to increased integration, separation between a bit line and a source line or between source lines is decreased, and the rate at which shorts occur may increase, thereby causing a significant reduction of yield.